module MAC_top_top(
    input Reset,
    //input Clk_in,
    input Clk_user,
    input Clk_125M,
    input Clk90,
    input   [11:0]  ram_dp_cfg_register,
    input dcm_locked,

    input rgmii_rx_clk,
    input [3:0] rgmii_rxd,
    input rgmii_rx_ctl,

    output phyrst_n,
    output rgmii_tx_clk,
    output [3:0] rgmii_txd,
    output rgmii_tx_ctl,
 

    input ff_rx_rdy,
    output [31:0] ff_rx_data,
    output [1:0] ff_rx_mod,
    output ff_rx_dsav,
    output ff_rx_dval,
    output ff_rx_sop,
    output ff_rx_eop,
    output [5:0] rx_err,
    output [10:0] frame_length,
    
    input [31:0] ff_tx_data,
    input [1:0] ff_tx_mod,
    input ff_tx_wren,
    input ff_tx_err,
    input ff_tx_sop,
    input ff_tx_eop,
    output ff_tx_rdy,
    output ff_tx_septy,
    output [5:0] Fifo_data_count
    );

reg phy_resetn_int;
reg [5:0]phy_reset_count;

//wires
//clocks
//wire Clk_125M;
//wire Clk90;
//wire dcm_locked;
//wire Clk_user;
//rst
wire glbl_rst_int;
wire glbl_rst_intn;
//
wire Crs;
wire Col;
wire [7:0] txd_from_mac;
wire tx_en_from_mac;
wire tx_er_from_mac;
wire [7:0] rxd_to_mac;
wire rx_dv_to_mac;
wire rx_er_to_mac;

wire rgmii_rx_clk_1;


wire rx_clk_to_mac;
wire tx_clk_to_mac;

wire CSB;
wire WRB;
wire [15:0] CD_in;
wire [15:0] CD_out;
wire [7:0] CA;
wire Mdio;
wire Mdc;

//---------------------------------------------
assign CSB = 1;
assign WRB = 1;
assign CD_in = 16'b0;
assign CA = 8'b0;

assign tx_clk_to_mac = rx_clk_to_mac;//
//---------------------------------------------
`ifdef FPGA_MODE
    IBUFG IBUFG_inst1(
        .O(rgmii_rx_clk_1   ),
        .I(rgmii_rx_clk     )
    );
`else
    assign rgmii_rx_clk_1 = rgmii_rx_clk ;
`endif

// IDELAYCTRL dlyctrl(
//     .RDY    (),
//     .REFCLK (Clk_user   ),
//     .RST    (Reset      )
// );
//---------------------------------------------
RESET_SYNC_FF2 glbl_reset_gen(
    .clk        (Clk_125M       ),
    .enable     (dcm_locked     ),
    .reset_in   (Reset          ),
    .reset_out  (glbl_rst_int   )
);
assign glbl_rst_intn = ~glbl_rst_int;

always@(posedge Clk_125M)
begin
    if(!glbl_rst_intn)
    begin
        phy_resetn_int <= 0;
        phy_reset_count  <= 0;
    end
    else
    begin
        if(!(&phy_reset_count))
            phy_reset_count <= phy_reset_count + 1;
        else
            phy_resetn_int <= 1;
    end
end
assign phyrst_n = phy_resetn_int;
//---------------------------------------------
// mac_rgmii_clk clk_gen(
//     .CLK_IN1_P      (Clk_in     ),
//     .CLK_OUT1       (Clk_125M   ),
//     .CLK_OUT2       (Clk_user   ),
//     .CLK_OUT4       (Clk90      ),
//     .RESET          (Reset      ),
//     .LOCKED         (dcm_locked )
// );
//---------------------------------------------
MAC_rgmii_v2_0_if rgmii_if(
    .tx_reset       (Reset          ),
    .rx_reset       (Reset          ),
    .rgmii_txd      (rgmii_txd      ),
    .rgmii_tx_ctl   (rgmii_tx_ctl   ),
    .rgmii_txc      (rgmii_tx_clk   ),
    .rgmii_rxd      (rgmii_rxd      ),
    .rgmii_rx_ctl   (rgmii_rx_ctl   ),
    .rgmii_rxc      (rgmii_rx_clk_1 ),
    .link_status    (),
    .clock_speed    (),
    .duplex_status  (),
    .txd_from_mac   (txd_from_mac   ),
    .tx_en_from_mac (tx_en_from_mac ),
    .tx_er_from_mac (tx_er_from_mac ),
    .tx_clk         (Clk_125M       ),
    .tx_clk90       (Clk90          ),
    .rxd_to_mac     (rxd_to_mac     ),
    .rx_dv_to_mac   (rx_dv_to_mac   ),
    .rx_er_to_mac   (rx_er_to_mac   ),
    .rx_clk         (rx_clk_to_mac  ),
    .crs_to_mac     (Crs            ),
    .col_to_mac     (Col            )
);
//---------------------------------------------
MAC_top U_MAC_top(
    .Reset              (Reset              ),
    .Clk_125M           (Clk_125M           ),
    .Clk_user           (Clk_user           ),
    .Clk_reg            (Clk_user           ),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .Speed              (),
    .ff_rx_rdy          (ff_rx_rdy          ),
    .ff_rx_data         (ff_rx_data         ),
    .ff_rx_mod          (ff_rx_mod          ),
    .ff_rx_sop          (ff_rx_sop          ),
    .ff_rx_eop          (ff_rx_eop          ),
    .ff_rx_dsav         (ff_rx_dsav         ),
    .ff_rx_dval         (ff_rx_dval         ),
    .rx_err             (rx_err             ),
    .frame_length       (frame_length       ),
    .ff_tx_data         (ff_tx_data         ),
    .ff_tx_mod          (ff_tx_mod          ),
    .ff_tx_sop          (ff_tx_sop          ),
    .ff_tx_eop          (ff_tx_eop          ),
    .ff_tx_wren         (ff_tx_wren         ),
    .ff_tx_err          (ff_tx_err          ),
    .tx_ff_uflow        (    ),
    .ff_tx_rdy          (ff_tx_rdy          ),
    .ff_tx_septy        ( ff_tx_septy       ),
    .Gtx_clk            (),
    .Rx_clk             (rx_clk_to_mac      ), // 就是Tx_clk
    .Tx_clk             (tx_clk_to_mac      ), // 来源于RGMII_if
    .Tx_er              (tx_er_from_mac     ),
    .Tx_en              (tx_en_from_mac     ),
    .Txd                (txd_from_mac       ),
    .Rx_er              (rx_er_to_mac       ),
    .Rx_dv              (rx_dv_to_mac       ),
    .Rxd                (rxd_to_mac         ),
    .Crs                (Crs                ),
    .Col                (Col                ),
    .CSB                (CSB                ),
    .WRB                (WRB                ),
    .CD_in              (CD_in              ),
    .CD_out             (CD_out             ),
    .CA                 (CA                 ),
    //.Mdio           (Mdio           ),
    //.Mdc            (Mdc            ),
    .Fifo_data_count    (Fifo_data_count    )
);
//---------------------------------------------
endmodule